Ph.D. in Computer Science at Rutgers University

Memory Hierachy - RAM

RAM is the "brain" for a whole system which stores everything the system need. This post will discuss about hardware structure of RAM and how it works.


SRAM, as we talked about in last post, is a fast storage but the cost is high; Transistors forms a static state. Typically, the access latency of L1 Cache is 4 cycles, L2 Cache 10 cycles and L3 Cache 40 cycles. The DRAM access time is around 100 cycles, in addition, due to the structure of RAM, it has to periodically refresh RAM cell to avoid data loss.


The left picture above shows the structure of 6T SRAM, as we've already discussed on it in very detail. The SRAM memory cell is a type of flip-flop circuit, which needs quite a lot of transistors. This means SRAM is expensive and has low storage density. The right picture above shows the structure of DRAM. A DRAM memory cell is base around a single capacitor. Charging and discharging this capacitor can store a '1' or a '0' in the cell. However, this capacitor will slowly leak away, and must be refreshed periodically. Because of this refresh process, DRAM uses more power, but it can achieve greater storage densities and lower unit costs compared to SRAM.